In recent years, power consumption by information processing apparatuses has rapidly increased. In the future, the reduction of energy consumption of the information processing apparatuses centered on Complementary Metal Oxide Semiconductor (CMOS) logic systems is expected to be more important than ever. In recent CMOS logic systems, such as microprocessors of personal computers (PC) and servers and system-on-chips (SoCs) of mobile terminals such as smartphones, transistors have been miniaturized and densely integrated, and thus the static or standby power, which is dissipation power during a standby mode owing to leak current, is distinctively large. As described above, increase in energy during a standby mode has been recognized as a serious problem. For example, the static power of the latest microprocessor has reached the same level as the dynamic power consumed while the CMOS works (operates). That is, such microprocessors consume the same level of power even without performing operations during the standby mode as that during operations. Therefore, the reduction of the static power has been an important issue in the CMOS logic systems.
Power Gating (PG) is a method for reducing static power, in which logic circuits are divided into blocks called power domains and individual power management (power restriction) of the power domains is performed by cutting off power supply. For the power management, used is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) switch called a power switch or a sleep transistor. Hereinafter, the power switch and the sleep transistor will be collectively referred to as a power switch. PG is now one of essential architectures for reducing energy in CMOS logic systems such as microprocessors and SoCs. Important factors for power saving (energy saving) effect in PG are the spatial granularity of the power domains (the size of the power domain) and the temporal granularity of execution of PG (the temporal frequency of execution of PG). The retention of information in the memory circuit inside the power domain limits the spatial and temporal granularity of PG. This is because important information stored in a memory circuit such as a register or a cash memory in the power domain is lost by cut of the power supply.
Non-volatile power gating (NVPG) resolves the aforementioned problems in conventional PG and achieves PG with optimal spatial and temporal granularity, which cannot be achieved only by a CMOS circuit. Thus, the NVPG is a technique that can reduce energy with high efficiency and drastically reduce power consumption during the standby mode. To achieve the NVPG, memory circuits such as cash memories, registers, or register files used in microprocessors or SoCs are replaced by non-volatile ones. These memory circuits are composed of bistable circuits such as Static Random Access Memories (SRAMs) or flip-flops (FFs). Addition of a non-volatile memory element such as a ferromagnetic tunnel junction (MTJ) to the bistable circuit can form a non-volatile bistable circuit such as a non-volatile SRAM (NV-SRAM) or a non-volatile FF (NV-FF).
Patent Document 1 discloses a memory circuit utilizing a cell including a bistable circuit and a non-volatile element. Called a non-volatile bistable circuit is a circuit that stores data in the bistable circuit to the non-volatile element and restores data in the non-volatile element to the bistable circuit. Patent Document 2 discloses a memory circuit that performs a normal SRAM operation, a sleep operation, a store operation, and power-off (shutdown) in a cell including a non-volatile bistable circuit. Patent Document 3 discloses a memory circuit that does not store data in the bistable circuit in the non-volatile element when the data stored in the bistable circuit and the data stored in the non-volatile element match.